Event description

Invited Lectures

The IEEE Greece CAS/SSC joint Chapter, in the frame of
the IEEE Circuits and System Society Distinguished Lecturer Program,
is inviting you in the lectures of:

Dr. Rajiv Joshi

Researcher at T. J. Watson research centre, IBM, NY,


“Technology Circuit Co-Design for Sub-nm Low Power Design”

The two lectures (joint events) will be given at:

1) University of Patras on Tuesday, December 6, 2016, at: 13:00, in the

Science and Technology Museum.

Information: Prof. George Alexiou, tel. 2610-996932, alexiou@ceid.upatras.gr Prof. Thanos Skodras, tel. 2610-996167,skodras@upatras.gr
2) Aristotle University of Thessaloniki on Thursday, December 8, 2016, at: 11:00, in the Amphitheater II of KEDEA.

Information: Prof. Alkis Hatzopoulos, tel. 2310-996305, 2310-996221, e-mail: alkis@eng.auth.gr

(There will be live webcasting and recording)

Abstract: Power has become the key driving force in processor design as the frequency scale-up is reaching saturation. In order to achieve low power system circuit and technology co-design is essential. This talk focuses on related technology and important circuit techniques for nanoscale VLSI circuits. Achieving low power and high performance simultaneously is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET and Trigates.

This talk consists of pros and cons analysis on technology from power perspective and various techniques to exploit lower power. As the technology pushes towards sub-22nm era, process variability and geometric variation in devices can cause variation in power. The reliability also plays an important role in the power-performance envelope. This talk also reviews the methodology to capture such effects and describes all the power components. All the key areas of low power optimization such as reduction in active power, leakage power, short circuit power and collision power are covered. Usage of clock gating, power gating, longer channel, multi-Vt design, stacking, header-footer device techniques and other methods are described for logic and memory. Finally the talk summarizes key challenges in achieving low power